An Area Efficient Pulse Triggered Flipflop Design under 90nm CMOS Technology

The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design an area efficient Low-Power Pulse- Triggered flip-flop. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The comparison of low power pulse triggered flip-flops such as Ep-DCO, MHLFF, ACFF, Ip-DCO, conditional enhancement scheme and signal feed through scheme. Logics are carried out and the best power-performance is obtained. Here simulations are done under 90nm technology and the results are tabulated below. In that signal feed through scheme is showing better output than the other flip-flops compared here